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michaltulacek

michaltulacek

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michaltulacek posts

Ending ball lightning captured on Iphone!


It was captured last year but I have not time to do some analysis yet.

And I am going to share more with you here... I have not seen something like that in my short life before. Of...

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GM UEFI development progress...#001


https://youtu.be/NFIahI_HWLE


Hello,

This is not April Fools' joke! :-)

...

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GMB v1.02 CPU/Cache/Memory Benchmark


Dear Patrons,

I would like to introduce GMB v1.02 CPU/Cache/Memory Benchmark

This is an example of MOV instruction test. It measures memory throughput.

It uses three me...

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Round #1: DDR5 OC via BCLK - four programs & one hour of testing

Dear Patrons,


Round #1: DDR5 OC via BCLK - four programs & one hour of testing...


I  have tested four testers (up-to-date):


GoldMemory v8...

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... different CPU architectures

Dear Patrons,

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I am working (x86 CPUs are executing lots of instructions) on special project and I almost finished an idea in my mind. I have to improve...

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CPU Visualization Art : an example


It would be nice to see CPU memory access in action :-) 



1 CPU / 16 variants of 1 algorithm

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486DX Cache Behaviour Benchmark v1

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AMD Geode LX 800 Cache Behaviour Benchmark v1

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Transmeta Crusoe TM5700 Cache Behaviour Benchmark v1

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GoldMemory PRO v8.01

Dear Patrons!


I would like to inform you that I am working on a new version of GoldMemory 8.01 for you , I will inform you when it will by released, again thank you for your suppor...

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Pentium 4 Memory disambiguation

Memory disambiguation is a set of techniques employed by high-performance out-of-order execution microprocessors that execute memory 

access instructions (loads and stores) out of progra...

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Intel Core i5-11400F Memory disambiguation

Memory disambiguation is a set of techniques employed by high-performance out-of-order execution microprocessors that execute memory 

access instructions (loads and stores) out of progra...

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AMD Ryzen 3 1200 Memory disambiguation

Memory disambiguation is a set of techniques employed by high-performance out-of-order execution microprocessors that execute memory access instructions (loads and stores) out of program order.

...

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Intel Core 2 Duo P9600 Memory disambiguation

Intel Core 2 Duo P9600 Memory disambiguation


Memory disambiguation is a set of techniques employed by high-performance out-of-order execution microprocessors that execute memory ac...

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CPU without cache 3D graph - 386DX (note: cache is on the motherboard)

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CPU cache 3D graph - an another example

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CPU cache 2D graph. It shows CPU AMD Ryzen 3700X data read troughput (algorithm: pre-calculated pointer chasing - address/data dependence - variant 1)

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Hello Patrons! I would like to show you first 3D graph of CPU cache/memory access. I am working on special videos as well. Michal Tulacek

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